Integrated circuits, such as Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs) or Electrically Erasable Programmable Read-Only Memories (EEPROMs), may undergo stress testing or "burn-in test" prior to shipment in an effort to detect defects in the integrated circuits. By subjecting a device to extreme operating conditions, such as, exposing the integrated circuit to abnormally high temperature and high voltage, the reliability and performance of the integrated circuits in normal operating conditions may be predicted. Conventional stress testing techniques are disclosed, for example, in U.S. Pat. Nos. 4,380,805; 5,363,333; and 5,590,079. U.S. Pat. No. 5,590,079 is hereby incorporated herein by reference.
A hierarchical word line structure (also referred to as a "split" or "segmented" word line structure) including main word lines and subword lines has been adopted for large capacity integrated circuit memory devices such as those having 16 Mb capacity or greater. Such a word line structure may use one conductive line as a main word line electrically connected to 4 or 8 subword lines of polysilicon. Accordingly, a high density (e.g., 64 Mb or greater) integrated circuit memory may be constructed without necessarily increasing the chip area. Examples of such word line structures are discussed in U.S. Pat. Nos. 5,148,401; 5,416,748; 5,761,135; and 5,764,585. U.S. Pat. No. 5,761,135 is hereby incorporated herein by reference.
As the level of integration of integrated circuits increases, there may also be a reduction in the spacing between adjacent conductive lines in the integrated circuits which may increase the likelihood of failures in the integrated circuits. In particular, bridges may form between conductive lines which may cause electrical shorts between the conductive lines, thereby causing the integrated circuit to fail. Accordingly, a need exists to further improve burn-in testing of integrated circuits.